The present invention relates to a frequency-locked loop circuit and a semiconductor integrated circuit incorporating the frequency-locked loop circuit.
Heretofore, low-power-consumption microcomputers (a microcomputer, a microcontroller, a microprocessor, and the like are hereinafter collectively called “a microcomputer”) incorporate a real time clock (RTC) function in many cases. In addition, it is necessary to improve the battery life of mobile devices, such as a smartphone and a digital still camera (DSC), which operate on a battery. Furthermore, white goods, such as a refrigerator and a washing machine, are required to be environmentally and economically friendly (eco-friendly) and to have an improved energy-saving performance. Under such circumstances, a microcomputer having a low voltage, low power consumption, and high performance tends to incorporate therein a clock dedicated chip RTC, which is an external component, and needs to be provided with an external crystal oscillator having a frequency of 32.768 KHz.
In an LSI (Large Scale Integration) of a microcomputer, a high-frequency clock is generated from a low-frequency clock of 32.768 KHz. A PLL (Phase Locked Loop: phase-locked loop circuit) is known as a typical technique for supplying the high-frequency clock to the inside of the LSI.
The PLL is a clock generator that multiplies an externally-supplied reference clock and supplies a high-frequency clock to the inside of the LSI. The PLL is conventionally designed with an LPF characteristic to be equal to 1/10 (min ¼) of that of the reference clock so as to realize a stable operation against noise and fluctuation of the reference clock (see Sung Tae Moon, Ari Yakov Valero-L'opez, and Edgar S'anchez-Sinencio “FULLY INTEGRATED FREQUENCY SYNTHESIZERS: A TUTORIAL”, International Journal of High Speed Electronics and Systems @ World Scientific Publishing Company). Accordingly, in many cases, the PLL is not used in the LSI that is supplied with only a low-frequency reference clock.
This is because when the PLL is used in the LSI that is supplied with only a low-frequency reference clock, the LPF characteristic thereof has a cut-off frequency of several KHz, and when the PLL is realized using monolithic capacitive elements and resistive elements, a large area is required, which is impractical in terms of cost. For example, when the input frequency is 32.768 KHz, a capacitance value of about 1 [nF] is required at about 3.2 KHz.
Thus, in place of the PLL, an FLL (Frequency Locked Loop) is widely applied as a clock generator capable of generating, as with the PLL, a high-frequency clock in an LSI with a small area.
While the FLL has an advantage of being capable of generating a high-frequency clock from a low-frequency clock with a small area, the FLL has a technical problem that a time for acquiring a frequency lock (a lock time or a set ring time) (hereinafter referred to as “lock time”) is long because a low-frequency clock is used as a reference.
For example, the Published Japanese Translation of PCT International Publication for Patent Application, No. 2004-520779 discloses a frequency locked-loop circuit that restores a clock from a signal transmitted through an optical fiber. This frequency locked-loop circuit includes a loop for locking a frequency and a loop for locking a phase, and has an object to simplify a dual-loop clock recovery circuit.
The FLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 2009-188699 achieves a reduction in lock time, which is a conventional problem to be solved. FIG. 19 is a block diagram showing a digital control oscillator of related art. As shown in FIG. 19, a digital control oscillator 510 includes a 2-input NAND gate 511 with one input terminal supplied with a reset signal Reset, and a digital control variable delay circuit 512 including N−1 delay cells each having a unit delay amount td. The number of delay stages N−1 of the digital control variable delay circuit 512 is set at a given value in the range from a minimum value “0” to a maximum value “31” according to the control by the digital control unit 520. Since the 2-input NAND gate 511 also has the unit delay amount td, a total delay time N·td of the 2-input NAND gate 511 and the digital control variable delay circuit 512 of the circuit type of a delay ring oscillation unit can be set within the range from a minimum delay time 1·td to a maximum delay time 32·td. This digital control oscillator can control frequencies by switching the number of delay stages.
In the FLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 2009-188699, a memory circuit is provided to the inside of an IP, or to an LSI that incorporates the IP, and a plurality of bits of design information or evaluation result information on the oscillation frequency of the digital control oscillator of the FLL circuit are stored into the memory circuit, thereby making it possible to significantly reduce the lock time.